# B5 Project Project Title: From CMOS integrated devices to the behavioral design of memristive circuits PI’s: Prof. Dr. Gerhard Kahmen, Prof. Dr. Andreas Mai, , Prof. Dr. habil. Christian Wenger Researcher(s): Max Uhlmann, Keerthi Dorai Swamy Reddy Dataset Name: MEMRES – Model Dataset Descriptions: Within this document a brief introduction to the Resistive RAM (RRAM) technology is given, together with a brief tutorial on how to set-up the MEMRES model adapted to the latest IHP's RRAM technology. Methodology: The MEMRES models are adapted to reproduce the static behavior of the RRAM technology. That is, the current response under voltage sweeps, not pulsed signals (dynamic response). In case the user is testing the MEMRES module under pulse signals, please see section 6 of this tutorial. Due to the fact that the forming operation is performed only once per device, the RRAM models included in the MEMRES module do not reproduce such operation. However, we recommend the user to consider the forming operation parameters for circuit design constrains. The devices are not formed during the fabrication process or before being delivered to the user. The user is referred to section 6 where the main forming parameters are listed. Setup: A brief explanation is given on how to set-up the MEMRES models. More precisely, how to build the previously mentioned 1T1R cell. Although in this module the mentioned structure is already provided (“1T1R” cell view), the user can follow this guide to get to know how to handle the models. It is assumed that the reader is using the SG13S design kit. Within below Figure, the schematic view of the 1T1R cell is showed. The circuit schematic will be developed in Cadence VirtuosoⓇ Schematic Editor. It can be appreciated that it is composed by the “MemTransistor” model and a NMOS transistor. Three input terminals supply the 1T1R cell: Vte makes reference to the top electrode terminal of the MemTransistor model, also known as BL, Vgate is connected to the gate terminal of the transistor (WL) and also to the vgate terminal of the MemTransistor and finally, Vsource and Bulk are directly connected to the source and bulk terminals of the NMOS transistor, respectively. This schematic is based on the 1T1R structure exposed in, as it can be appreciated. For clarification purpose, the vgate terminal of the MemTransistor cell does not exist in a real 1T1R structure. This terminal is exclusively consider in simulations in order to enable the multilevel function of the structure. For further details, the reader is referred to [^1]. :::{figure-md} fig-target :class: align-center ```{image} ../_static/B5_figure2.png :alt: :width: 275px ``` 1T1R cell circuit schematic in VirtuosoⓇ Schematic Editor. ::: Parameters: The table below summarizes the main MEMRES electrical parameters. The range of values provided are extracted from ISPVA programming tests over 4096 1T1R devices embedded in 4 kbit arrays. :::{figure-md} fig-target :class: align-center ```{image} ../_static/B5_figure1.png :alt: :width: 475px ``` Electrical parameters to program multilevel 1T1R cells using pulsed signals. ::: Click here to access the dataset. References: [^1]: Perez-Bosch Quesada, Emilio, Rocio Romero-Zaliz, Eduardo Perez, Mamathamba Kalishettyhalli Mahadevaiah, John Reuben, Markus Andreas Schubert, Francisco Jimenez-Molinos, Juan Bautista Roldan, and Christian Wenger (2021). Toward reliable compact modeling of multilevel 1T-1R RRAM devices for neuromorphic systems. Electronics, 10(6), 645. doi:10.3390/electronics10060645